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The BERTScope BSX-series Bit Error Rate Tester introduces a receiver test platform capable of supporting emerging Gen4 standards and beyond. With the addition of powerful data processing and internal Tx equalization, the BERTScope supports protocol-based handshaking and synchronization with your device under test (DUT), including interactive link training at data rates up to 32 Gb/s. The BSX-series shortens the time to debug physical layer and link training issues, and provides the quickest path to compliance for a broad range of standards.
- Data rate range
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- BSX125
- 0.6 to 12.5 Gb/s
- BSX240
- 1 to 24 Gb/s
- BSX320
- 1 to 32 Gb/s
- Format
- NRZ
- Polarity
- Normal or inverted
- Variable cross over
- 30 to 70%
- Patterns
-
- Hardware patterns
- Industry-standard Pseudo-random (PRBS) of the following types: 2n - 1 where n = 7, 11, 15, 20, 23, 31
- RAM patterns
- 128 bits to 512 Mbits total with support for 128 pattern sequencer states
- Library
- Wide variety including SONET/SDH, Fibre Channel based such as k28.5, CJTPAT; 2n patterns where n = 3, 4, 5, 6, 7, 9; Mark Density patterns for 2n where n = 7, 9, 23; and many more
- Pattern sequencer
- Implements indirect access to pattern memory
- Modes
- Bit mode – no protocol processing applied Protocol-aware mode – protocol processing applied for supported protocols
- Sequencer states
- Up to 128 pattern sequencer states
- Loop levels
- Two levels (up to 1 M iterations per loop)
- Pattern segment size
- Minimum 128 bits, single bit granularity up to maximum memory size.
- Protocol mode
- Operates in units of protocol blocks: For PCIe Gen3/Gen4, a single 128b/130b block For USB 3.1 SSP, a single128b/132b block For 8b/10b, from 1 to16 8b/10b symbols
- Protocol processing
- Protocol-aware mode processing includes: Packaging of symbols into protocol blocks Symbol encoding (8b/10b) Data scrambling (all protocols) DC balancing (PCIe Gen3/4, USB 3.1 SSP)
- Error insertion
-
- Length
- 1, 2, 4, 8, 16, 32, 64 bit bursts
- Frequency
- Single or repetitive
- Pattern Generation and Error Analysis up to 32 Gb/s
- Optional built-in 4-tap Tx equalization with support for interactive link training
- Protocol-oriented and bit-oriented multi-chain pattern sequencing with enhanced pattern/sequence editor
- User-defined detector pattern matching with stimulus-response feedback
- Patented Error Location Analysis™ goes beyond BER measurement to provide insight into the sources of errors through analysis of correlations and deterministic error patterns
- Optional Forward Error Correction analysis provides for simulation of post-FEC error rate based upon measured error location patterns
- Integrated Eye Diagram Analysis with BER Correlation including Mask Testing, Jitter Peak, BER Contour
- Optional Jitter Map Comprehensive Jitter Decomposition - with Long Pattern (i.e. PRBS-31) Jitter
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