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The BERTScope Clock Recovery CR Series advanced architecture measures and displays the PLL frequency response from 100 kHz to 12 MHz; the highest loop bandwidth available for jitter testing jitter testing on the market today. The first clock recovery instruments to allow full control of parameters including loop bandwidth, peaking/damping, and roll off.
Key specifications
Data inputs/outputs
| Characteristic | CR125A | CR175A | CR286A | CR286A Option HS |
| Input sensitivity | 100 mV single ended (typical) 50 mV differential (typical) | 40 mV single ended (typical) 20 mV differential (typical) | ||
| Input data rate coverage | 150 Mb/s to 12.5 Gb/s | 150 Mb/s to 17.5 Gb/s | 150 Mb/s to 28.6 Gb/s | 150 Mb/s to 28.6 Gb/s |
| Data insertion loss | 2 dB (min), 2.6 dB (typical), 3 dB (max), up to 12.5 Gb/s 1 | - | ||
| Data input voltage range | -5 V (min), +5 V (max) | -5 V (min), +5 V (max), 1 Vp-p (max) | ||
| Measured edge density accuracy | ±1%, up to 14.3 Gb/s, ±3% >14.3 Gb/s | |||
| Equalization range | 0 to 10 dB | |||
| Data output | Up to 12.5 Gb/s 1 | - | ||
Clock and subrate clock outputs
| Characteristic | CR125A | CR175A | CR286A | CR286A Option HS |
| Loop bandwidth | 100 kHz to 12 MHz 200 kHz to 12 MHz above 14.3 GHz - up to 24 MHz with Option XLBW ext. loop BW | |||
| Peaking | 0-6 dB, 500 kHz - 12 MHz 0-5 dB, 12 MHz - 24 MHz with Option XLBW | |||
| Intrinsic jitter (typical) | 250 fs | |||
| Clock output range | Full-rate clock for input data rates to 14.3 Gb/s Half-rate clock for input data rates >14.3 Gb/s | |||
| Sub-rate divider ratios | For input data rate to 14.3 Gb/s: Full rate divided by 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 25, 28, 30, 32, 35, 36, 40, 42, 45, 48, 49, 50, 54, 56, 60, 63, 64, 70, 72, 80, 81, 90, 100, 108, 112, 120, 126, 128, 140, 144, 160, 162, 168, 180, 192, 196, 200, 216, 224, 240, 252, 256, 280, 288, 320, 324, 336, 360, 384, 392, 432, 448, 504, 512, 576, 648 For input data rate >14.3 Gb/s: Full rate divided by 2, 4, 8, 10, 12, 14, 16, 18, 20, 24, 28, 32, 36, 40, 48, 50, 56, 60, 64, 70, 72, 80, 84, 90, 96, 98, 100, 108, 112, 120, 126, 128, 140, 144, 160, 162, 180, 200, 216, 224, 240, 252, 256, 280, 288, 320, 324, 336, 360, 384, 392, 400, 432, 448, 480, 504, 512, 560, 576, 640, 648, 672, 720, 768, 784, 864, 896, 1008, 1024, 1152, 1296 | |||
- 150 Mb/s to 28.6 Gb/s with continuous data rate coverage to include Next-generation I/Os including PCIe 3.0, 10GBASE-KR, 16xFC, 25/28 G CEI, and 100GBASE-LR-4/100GBASE-ER-4
- Full and divided clock outputs with selectable divide ratios. Full-rate clock output up to 14.3 Gb/s, half-rate clock output from 14.3 Gb/s to 17.5 and 28.6 Gb/s
- Optional PCIe 2.5, 5, and 8 gb/s PLL loop analysis (Also requires jitter analysis option)
- CR175A and CR286A offer optional higher-sensitivity data inputs with clock recovery on signals as small as 40 mV amplitude (single ended), 20 mV amplitude (differential) – no DC-coupled data through path with this option
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